The research is expected to catalyze further innovations in the area of extensible nano-manufacturing and possibly be integrated into the manufacturing process in the next seven to 10 years.

This advance could help extend the manufacturability of semiconductors beyond conventional lithography methods, with the potential for enabling electronics makers to meet the demand for smaller, faster and cheaper devices.

The ever-shrinking lithography processes for semiconductors have produced dramatic size, speed and cost benefits for the electronics industry. However, the industry faces certain physical and economic constraints as it moves to smaller transistor scales, or nodes. In particular, the industry has yet to find a manufacturing solution to patterning feature sizes beyond the 22nm node.

In recent years, researchers have begun to look at block copolymers, an organic material that is compatible with conventional semiconductor manufacturing processes, because a thin film of it, under the right conditions, can self-assemble into regular arrays of holes on the order of 20nm or smaller in diameter. This tiny, self-assembled swiss cheese of block copolymer can act as a stencil for creating electrical contacts to very small semiconductor devices.

Previous attempts at using block polymers have fallen short because the self-assembled holes were not aligned to existing electrical features on the semiconductor wafer. Now, the SRC-sponsored work by researchers from Stanford University and TSMC has produced the industry’s first functional devices and circuits that employ diblock copolymer patterning for sub-22nm CMOS technologies on a full wafer scale.

Philip Wong, a professor of electrical engineering at Stanford University, said: “We believe this development will help to bring self-assembly closer to broad application in the semiconductor industry and will help increase the use of nano-technology for advancements in electronics for years to come.”

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